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? semiconductor components industries, llc, 2009 april, 2009 ? rev. 8 1 publication order number: nb6l11/d nb6l11 2.5 v/3.3 v multilevel input to differential lvpecl/lvnecl 1:2 clock or data fanout buffer/translator the nb6l11 is an enhanced differential 1:2 clock or data fanout buffer/translator. the device has the same pinout and is functionally equivalent to the lvel11, ep11, lvep11 devices. moreover, the device is optimized for the systems that require low skew, low jitter and low power consumption. differential input can be configured to accept single ? ended signal by applying an external reference voltage to unused complementary input pin. input accept lvnecl, lvpecl, lvttl, lvcmos, cml, or lvds. the outputs are 800 mv ecl signals. features ? input clock frequency 6 ghz ? input data rate 6 gb/s ? low 14 ma typical power supply current ? 150 ps typical propagation delay ? 5 ps typical within device skew ? 75 ps typical rise/fall times ? pecl mode operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? necl mode op rating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.465 v ? open input default state ? q outputs will default low with inputs open or at v ee ? lvds, lvpecl, lvnecl, lcmos, lvttl and cml input compatible ? pb ? free packages are available 6l11 alyw a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. so ? 8 d suffix case 751 marking diagrams* tssop ? 8 dt suffix case 948r 6l11 alyw 1 8 1 8 1 8 1 8 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information (note: microdot may be in either location)
nb6l11 http://onsemi.com 2 1 2 3 4 5 6 7 8 d v ee v cc figure 1. pinout (top view) and logic diagram q0 d q1 q1 q0 r 2 r 2 r 1 r 1 table 1. pin description pin name i/o default state description 1 ? non ? inverted differential clock/data output 0. typically termin- ated with 50 resistor to v tt = v cc ? 2 v. 2 q0 ecl output ? inverted differential clock/data output 0. typically terminated with 50 resistor to v tt = v cc ? 2 v. 3 q1 ecl output ? non ? inverted differential clock/data output 1. typically termin- ated with 50 resistor to v tt = v cc ? 2 v. 4 q1 ecl output ? inverted differential clock/data output 1. typically terminated with 50 resistor to v tt = v cc ? 2 v. 5 v ee ? ? negative power supply voltage 6 d lvds, cml, lvpecl, lvnecl, lvcmos, lvttl input high inverted differential clock/data input. internal 37.5 k to v cc and 75 k to v ee . 7 d lvds, cml, lvpecl, lvnecl, lvcmos, lvttl input low non ? inverted differential clock/data input. internal 75 k to v cc and 37.5 k to v ee . 8 v cc ? ? positive power supply voltage table 2. attributes characteristics value internal input pulldown resistor 37.5 k internal input pullup resistor 75 k esd protection human body model machine model charged device model > 2 kv > 100 v > 1 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg soic ? 8 tssop ? 8 level 1 level 1 level 1 level 3 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 167 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
nb6l11 http://onsemi.com 3 table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ? 3.6 v v i positive input voltage negative input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ? 3.6 v v v inpp differential input voltage |d ? d | v cc ? v ee 2.8 v v cc ? v ee 2.8 v 2.8 |v cc ? v ee | v i out output current continuous surge 25 50 ma ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 8 soic ? 8 190 130 c/w c/w jc thermal resistance (junction ? to ? case) standard board soic ? 8 41 to 44 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 8 tssop ? 8 185 140 c/w c/w jc thermal resistance (junction ? to ? case) standard board tssop ? 8 41 to 44 c/w t sol wave solder standard pb ? free 3 sec @ 248 c 3 sec @ 260 c 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nb6l11 http://onsemi.com 4 table 4. dc characteristics, pecl v cc = 2.5 v, v ee = 0 v (note 4) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current (note 5) 5 14 20 5 14 20 5 14 20 ma v oh output high voltage (note 6) 1350 1450 1550 1400 1500 1600 1450 1550 1650 mv v ol output low voltage (note 6) 565 725 870 630 765 920 690 825 970 mv differential input driven single ? ended (figures 14, 16) (note 7) v th input threshold reference voltage range (note 2) 1125 v cc ? 75 1125 v cc ? 75 1125 v cc ? 75 mv v ih single ? ended input high voltage v th +75 v cc v th +75 v cc v th +75 v cc mv v il single ? ended input low voltage v ee v th ? 75 v ee v th ? 75 v ee v th ? 75 mv differential inputs driven differentially (figures 15, 17) (note 8) v ihd differential input high voltage 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage v ee v cc ? 75 v ee v cc ? 75 v ee v cc ? 75 mv v cmr input common mode range (differential cross ? point voltage) (note 3) 950 v cc ? 38 950 v cc ? 38 950 v cc ? 38 mv v id differential input voltage (v ihd ? v ild ) 75 2500 75 2500 75 2500 mv i ih input high current d d 50 10 150 150 50 10 150 150 50 10 150 150 a i il input low current d d ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. v th is applied to the complementary input when operating in single ? ended mode. 3. v cmr minimum varies 1:1 with v ee , v cmr maximum varies 1:1 with v cc . 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to ? 1.3 v. 5. all input and output pins left open. 6. all loading with 50 to v cc ? 2.0 v. 7. v th , v ih , and v il parameters must be complied with simultaneously. 8. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
nb6l11 http://onsemi.com 5 table 5. dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 11) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current (note 12) 5 14 20 5 14 20 5 14 20 ma v oh output high voltage (note 13) 2150 2250 2350 2200 2300 2400 2250 2350 2450 mv v ol output low voltage (note 13) 1365 1525 1670 1430 1565 1720 1490 1625 1770 mv differential input driven single ? ended (figures 14, 16) (note 14) v th input threshold reference voltage range (note 9) 1125 v cc ? 75 1125 v cc ? 75 1125 v cc ? 75 mv v ih single ? ended input high voltage v th +75 v cc v th +75 v cc v th +75 v cc mv v il single ? ended input low voltage v ee v th ? 75 v ee v th ? 75 v ee v th ? 75 mv differential inputs driven differentially (figures 15, 17) (note 15) v ihd differential input high voltage 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage v ee v cc ? 75 v ee v cc ? 75 v ee v cc ? 75 mv v cmr input common mode range (differential cross ? point voltage) (note 10) 950 v cc ? 38 950 v cc ? 38 950 v cc ? 38 mv v id differential input voltage (v ihd ? v ild ) 75 2500 75 2500 75 2500 mv i ih input high current d d 50 10 150 150 50 10 150 150 50 10 150 150 a i il input low current d d ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. v th is applied to the complementary input when operating in single ? ended mode. 10. v cmr minimum varies 1:1 with v ee , v cmr maximum varies 1:1 with v cc . 11. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ? 2.2 v. 12. all input and output pins left open. 13. all loading with 50 to v cc ? 2.0 v. 14. v th , v ih , and v il parameters must be complied with simultaneously. 15. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
nb6l11 http://onsemi.com 6 table 6. dc characteristics, necl v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v (note 18) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current (note 19) 5 14 20 5 14 20 5 14 20 ma v oh output high voltage (note 20) ? 1150 ? 1050 ? 950 ? 1100 ? 1000 ? 900 ? 1050 ? 950 ? 850 mv v ol output low voltage (note 20) ? 1935 ? 1775 ? 1630 ? 1870 ? 1735 ? 1580 ? 1810 ? 1675 ? 1530 mv differential input driven single ? ended (figures 14, 16) (note 21) v th input threshold reference voltage range (note 16) v ee +1125 v cc ? 75 v ee +1125 v cc ? 75 v ee +1125 v cc ? 75 mv v ih single ? ended input high voltage v th +75 v cc v th +75 v cc v th +75 v cc mv v il single ? ended input low voltage v ee v th ? 75 v ee v th ? 75 v ee v th ? 75 mv differential inputs driven differentially (figures 15, 17) (note 22) v ihd differential input high voltage v ee +1200 v cc v ee +1200 v cc v ee +1200 v cc mv v ild differential input low voltage v ee v cc ? 75 v ee v cc ? 75 v ee v cc ? 75 mv v cmr input common mode range (differential cross ? point voltage) (note 17) v ee +950 v cc ? 38 v ee +950 v cc ? 38 v ee +950 v cc ? 38 mv v id differential input voltage (v ihd ? v ild ) 75 2500 75 2500 75 2500 mv i ih input high current d d 50 10 150 150 50 10 150 150 50 10 150 150 a i il input low current d d ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 ? 150 ? 150 ? 5 ? 30 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. v th is applied to the complementary input when operating in single ? ended mode. 17. v cmr minimum varies 1:1 with v ee , v cmr maximum varies 1:1 with v cc 18. input and output parameters vary 1:1 with v cc . 19. input and output pins left open. 20. all loading with 50 to v cc ? 2.0 v. 21. v th , v ih , and v il parameters must be complied with simultaneously. 22. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
nb6l11 http://onsemi.com 7 table 7. ac characteristics v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v (note 23) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude f in 3 ghz (see figures 2 & 3 ) f in 6 ghz 480 270 700 300 480 270 700 300 480 270 700 300 mv f data maximum operating data rate 6 gb/s t plh , t phl propagation delay to output differential @ 1 ghz d to q, q 110 150 190 110 150 200 120 160 220 ps t skew duty cycle skew within device skew (note 24) device ? to ? device skew 2 5 15 10 15 60 2 5 15 10 15 60 2 5 15 10 15 60 ps t jitter rms random clock jitter (note 25) f in 6 ghz peak ? to ? peak data dependent jitter (note 26) f in 6 gb/s 0.2 2 1 12 0.2 2 1 12 0.2 2 1 12 ps v inpp input voltage swing / sensitivity (differential configuration) (note 27) 75 700 2500 75 700 2500 75 700 2500 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 30 75 120 30 75 120 30 75 120 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 23. measured using a 800 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 24. see figure 13 t skew = |t plh ? t phl | for a nominal 50% dif ferential clock input waveform. skew is measured between outputs under identical transitions and conditions @ 1 ghz. 25. additive rms jitter with 50% duty cycle clock signal at 6 ghz. 26. additive peak ? to ? peak data dependent jitter with nrz prbs 2 23 ? 1 data rate at 6 gb/s. 27. v inpp(max) cannot exceed v cc ? v ee (applicable only when v cc ? v ee < 2500 mv). input voltage swing is a single ? ended measurement operating in differential mode 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 12 45678 3 output voltage amplitude (v) figure 2. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature at v cc ? v ee = 3.3 v input clock frequency (ghz) 85 c ? 40 c 25 c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 12345678 output voltage amplitude (v) ? 40 c 85 c 25 c figure 3. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature at v cc ? v ee = 2.5 v input clock frequency (ghz)
nb6l11 http://onsemi.com 8 figure 4. typical phase noise plot at f carrier = 156.25 mhz figure 5. typical phase noise plot at f carrier = 622.08 mhz figure 6. typical phase noise plot at f carrier = 1.5 ghz figure 7. typical phase noise plot at f carrier = 2 ghz the above phase noise plots captured using agilent e5052a show additive phase noise of the nb6l11 device at frequencies 156.25 mhz, 622.08 mhz, 1.5 ghz and 2 ghz respectively at an operating voltage of 3.3 v in room temperature. the rms phase jitter contributed by the device (integrated between 12 khz and 20 mhz; as shown in the shaded region of the plot) at each of the frequencies is 75 fs, 12 fs, 6 fs and 4 fs respectively. the input source used for the phase noise measurements is agilent e8663b.
nb6l11 http://onsemi.com 9 figure 8. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (total system pk ? pk jitter is 17 ps. device pk ? pk jitter contribution is 4 ps) time (64 ps/div) output voltage amplitude (100 mv/div) figure 9. typical output waveform at 6.125 gb/s with prbs 2 23 ? 1 (total system pk ? pk jitter is 20 ps. device pk ? pk jitter contribution is 5 ps) time (32 ps/div) output voltage amplitude (100 mv/div) note: v cc ? v ee = 3.3 v; v in = 700 mv; t a = 25 c. 110 130 150 170 190 210 2.375 2.5 3.3 3.465 85 c ? 40 c 25 c propagation delay (ps) figure 10. propagation delay versus power supply voltage and temperature power supply voltage (v) 30 40 50 60 70 80 90 100 110 120 2.375 2.5 3.3 3.465 85 c ? 40 c 25 c figure 11. rise/fall time versus power supply voltage and temperature power supply voltage (v) rise/fall time (ps) 5 8 11 14 17 20 ? 40 25 85 v cc ? v ee = ? 3.465 v v cc ? v ee = ? 2.375 v figure 12. i ee current versus temperature and power supply voltage temperature ( c) i ee current (ma)
nb6l11 http://onsemi.com 10 figure 13. ac reference measurement d d q q t phl t plh v inpp (d) = v ih (d) ? v il (d) v inpp (d ) = v ih (d ) ? v il (d ) v outpp (q) = v oh (q) ? v ol (q) v outpp (q ) = v oh (q ) ? v ol (q ) d v th d v th figure 14. differential input driven single ? ended d d figure 15. differential inputs driven differentially v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th v ihdmax v ildmax v ihdmin v ildmin v ihdtyp v ildtyp v id = v ihd ? v ild v cmr v cc v cmmax v cmmax gnd figure 16. v th diagram figure 17. v cmr diagram figure 18. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v
nb6l11 http://onsemi.com 11 ordering information device package shipping ? nb6l11d soic ? 8 98 units / rail nb6l11dg soic ? 8 (pb ? free) 98 units / rail nb6l11dr2 soic ? 8 2500 / tape & reel nb6l11dr2g soic ? 8 (pb ? free) 2500 / tape & reel NB6L11DT tssop ? 8 100 units / rail NB6L11DTg tssop ? 8 (pb ? free) 100 units / rail NB6L11DTr2 tssop ? 8 2500 / tape & reel NB6L11DTr2g tssop ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
nb6l11 http://onsemi.com 12 package dimensions soic ? 8 nb case 751 ? 07 issue ah seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
nb6l11 http://onsemi.com 13 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop ? 8 dt suffix plastic tssop package case 948r ? 02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb6l11/d eclinps is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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